The present invention relates generally to electrically erasable, programmable read only memory (EEPROM) arrays and methods for operation thereof, and more particularly, to refreshing the threshold voltage of bits of cells in such arrays.
EEPROM arrays are utilized for storage of data. Typically, the data stored therein can be changed, either by programming or erasing, multiple times over the lifetime of the array. As in all non-volatile memory arrays, each cell is individually programmed; however, in contrast to either erasable, programmable read only memory (EPROM) or FLASH arrays, in EEPROM arrays each cell can also be individually erased.
Typical memory uses a single bit per cell, wherein electrical charge is stored on the floating gate of each cell. Within each cell, two possible voltage levels exist. The levels are controlled by the amount of charge that is stored on the floating gate; if the amount of charge on the floating gate is above a certain reference state, the cell is considered to be in a different state. Accordingly, each cell is characterized by a specific threshold voltage (Vt). Programming the cell increases threshold voltage Vt, whereas erasing the cell decreases threshold voltage Vt.
Non-volatile memory arrays comprise rows and columns of memory cells electrically connected to word lines (rows of the array) and bit lines (columns). Each memory cell is connected to one word line and at least one bit line. Another terminal of the memory cell is connected either to another bit line (in which case, one of the bit lines is called the drain line and the other is the source line), or to a common line, such as a common source ground, depending on the array architecture. Programming or erasing an individual cell requires application of certain voltages to the word line and bit lines.
Generally, when programming or erasing a cell, one or more of the neighboring cells may also be affected by the programming/erasing operation, causing thereto a possible change in their threshold voltage. This unwanted change in threshold voltage of unselected cells is known in the art as the disturb problem, herein a xe2x80x9cdisturbxe2x80x9d. A similar effect also occurs during a read operation. However, due to the relative weakness of the applied voltage levels, the effect during read is significantly smaller. A standard prior art solution to the disturb problem in EEPROM arrays is to use two transistors per memory bit of the array, i.e., in addition to the memory transistor, a select transistor is also incorporated per cell. The select transistor usually disconnects the drain of the memory transistors of the unselected word lines from the drain voltages used in the programming/erasing operations. The use of a select transistor per cell, however, significantly increases the area of the memory array.
There are other phenomena that affect the threshold voltage of memory cells. For example, the memory cell has a certain retention of charge that degrades with time, meaning that the programmed state of the cell deteriorates over the course of time. At elevated operating temperatures, this deterioration is further accelerated.
The present invention seeks to provide a novel technique for combating changes in threshold voltage of memory cells. In accordance with a preferred embodiment of the present invention, the threshold voltage of a memory cell in a programmed state that has been lowered, such as a result of program or erase disturbs or retention problems, is refreshed (that is, re-elevated) to a predetermined level. This is preferably accomplished by monitoring the threshold voltage level of the bit or bits of the cells, comparing with at least one predetermined threshold voltage level, and applying a set of programming voltages that raise the threshold voltage level by the desired amount. In addition, the threshold voltage of a memory cell in an erased cell that has been raised, due to some operation on the array, for example, may be refreshed (i.e., re-lowered) to a predetermined level, such as by applying a set of erasing voltages that lower the threshold voltage by the desired amount.
In general, after performing an operation on bits of a slice of an EEPROM array, the threshold voltages of a portion of or all the bits of the entire slice are monitored and compared with the level prior to the operation. For example, after programming bits of a slice of the EEPROM array, the threshold voltage levels of all of the bits of the entire slice may be monitored and compared with the preceding levels. Generally, after erasing bits of the slice, the threshold voltages of those bits sharing the same bit line as the selected bits that were erased may be monitored. Those bits that need to be refreshed may then be programmed to the desired threshold voltage level.
The refresh voltages may be applied one bit at a time or to more than one bit at a time, until all the bits are refreshed. If desired, the threshold voltage may even be refreshed to a level below or above the original level, by applying a different set of voltages or by changing the duration of the voltage application.
There is thus provided in accordance with a preferred embodiment of the present invention, a method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including refreshing a threshold voltage of a bit of a memory cell in an EEPROM array, the threshold voltage being different than a previous threshold voltage, by restoring the threshold voltage of the bit at least partially back to the previous threshold voltage.
In accordance with a preferred embodiment of the present invention, the method further includes comparing the threshold voltage of said bit with the previous threshold voltage, wherein said refreshing is performed if the threshold voltage of said bit has crossed over a predetermined level.
Further in accordance with a preferred embodiment of the present invention the comparing is performed after a predetermined number of operations performed on the array, or alternatively, after a predetermined amount of time.
Still further in accordance with a preferred embodiment of the present invention, the method includes performing an operation on at least one bit of a selected memory cell of the array, the operation including at least one of programming and erasing, and comparing the threshold voltage of at least one bit of at least one other memory cell in the EEPROM array. If that at least one bit (i.e., the at least one disturbed bit) is supposed to be in a programmed state, then its threshold voltage is re-elevated at least partially to the previous threshold voltage level. If the disturbed bit is supposed to be in an erased state, then its threshold voltage is re-lowered at least partially to the previous threshold voltage level.
Further in accordance with a preferred embodiment of the present invention, the method includes, before performing the operation, recording the threshold voltage of the at least one bit of the at least one other memory cell in the EEPROM array.
Still further in accordance with a preferred embodiment of the present invention the array includes a multiplicity of the memory cells, wherein each memory cell is electrically connected to a word line and to two bit lines, one of the bit lines serving as a source and the other bit line serving as a drain.
In accordance with a preferred embodiment of the present invention, the method further includes placing at least one column of the memory cells between a pair of isolation zones, the isolation zones defining therebetween a slice of word lines and bit lines.
Further in accordance with a preferred embodiment of the present invention the memory cells are NROM memory cells.
Still further in accordance with a preferred embodiment of the present invention the operation on the bit of the selected memory cell of the array is performed while applying an inhibit gate voltage to the word line of an unselected memory cell.